Kaffee, Tea, Kakao and More 3.0

[Thor Branke]

Elöllah!

[karlos3]

Niom!

[michi27]

Mein Windows 10 will mich heute auf "Eine neue Reise" vorbereiten. Hoffentlich nicht die letzte ...

[miezi71]

kcütshürF muz nwolC arruH

hcua hteg sdnebA

[gkj43]

Moin ihrs!

[Thor Branke]

erle!

Mein Windows 10 will mich heute auf "Eine neue Reise" vorbereiten.

Schon spaßig, das 18 Monate vor Schichtende zu verschicken.

Habe neulich mit Coreinfo (https://learn.microsoft.com/de-de/sysin ... s/coreinfo) gecheckt, ob mein Prozesser von 2013/14 Popcount-fähig ist, was ja eine Begrenzung für die Verwendbarkeit von Windows 11 24H2 ist. Obwohl 10 Jahre alt, berherrscht er das. Ich muss nur die beiden anderen Gängelfaktoren (TPM & Secure Boot) umgehen und kann dann auf meinem alten PC Windows 11 verwenden. Es sei denn, MS fällt bis 25H2 noch 'ne andere Gängelei ein.

[Foren-Rentner™]

@ all

[Schalker]

Moin Atall

[michi27]

Habe neulich mit Coreinfo (https://learn.microsoft.com/de-de/sysin ... s/coreinfo) gecheckt, ob mein Prozesser von 2013/14 Popcount-fähig ist, was ja eine Begrenzung für die Verwendbarkeit von Windows 11 24H2 ist. ...

Nie von gehört, was soll das sein (und bringen)? Kann mit dem Output nichts anfangen:

Code: Alles auswählen

C:\Proggis\CoreInfo>Coreinfo64

Coreinfo v3.6 - Dump information on system CPU and memory topology
Copyright (C) 2008-2022 Mark Russinovich
Sysinternals - www.sysinternals.com


Intel(R) Core(TM) i5-3570K CPU @ 3.40GHz
Intel64 Family 6 Model 58 Stepping 9, GenuineIntel
Microcode signature: 00000021
HTT             *       Hyperthreading enabled
CET             -       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        -       User-mode CET Allowed
HYPERVISOR      -       Hypervisor is present
VMX             *       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            -       Supports Supervisor Mode Access Prevention
PAGE1GB         -       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            -       Supports AVX2 instruction extensions
AVX-512-F       -       Supports AVX-512 Foundation instructions
AVX-512-DQ      -       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   -       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      -       Supports AVX-512 conflict detection instructions
AVX-512-BW      -       Supports AVX-512 byte and word instructions
AVX-512-VL      -       Supports AVX-512 vector length instructions
FMA             -       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          -       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            -       Supports bit manipulation extensions 1
BMI2            -       Supports bit manipulation extensions 2
ADX             -       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           -       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           -       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          *       Can write history of 64-bit branch addresses
DS              *       Implements memory-resident debug buffer
DS-CPL          *       Supports Debug Store feature with CPL
PCID            *       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            *       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            *       Supports disabling task priority messages

EIST            *       Supports Enhanced Intel Speedstep
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             *       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).
Maximum implemented address width: 48 bits (virtual), 36 bits (physical).

Processor signature: 000306A9

Logical to Physical Processor Map:
*---  Physical Processor 0
-*--  Physical Processor 1
--*-  Physical Processor 2
---*  Physical Processor 3

Logical Processor to Socket Map:
****  Socket 0

Logical Processor to NUMA Node Map:
****  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*---  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
*---  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
*---  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
****  Unified Cache       1, Level 3,    6 MB, Assoc  12, LineSize  64
-*--  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
-*--  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
-*--  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
--*-  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
--*-  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
--*-  Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64
---*  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
---*  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
---*  Unified Cache       4, Level 2,  256 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
****  Group 0

-> POPCNT * Supports POPCNT instruction - is' es das?
Dann wäre aber auch Hyper Threading enabled, obwohl das ein alter Quad-Core OHNE HT ist.

[Thor Branke]

Nie von gehört, was soll das sein (und bringen)? Kann mit dem Output nichts anfangen:

Code: Alles auswählen

[b][u]POPCNT          *       Supports POPCNT instruction[/u][/b]

-> POPCNT * Supports POPCNT instruction - is' es das?
Dann wäre aber auch Hyper Threading enabled, obwohl das ein alter Quad-Core OHNE HT ist.

Genau, das ist es. Das Sternchen zeigt an, dass der Prozessor das kann.
Meine Quelle: Windows 11 24H2 CPU auf POPCNT prüfen mit Coreinfo | EINFACH ERKLÄRT
https://www.youtube.com/watch?v=UN9KQ5jQNtA

[Schalker]

Gute Nacht

[Foren-Rentner™]

@ all

[Schalker]

Das kann ich toppen

[Foren-Rentner™]

, aber die Spielereien haben wir schon vor 20 Jahren mitgemacht!

[Thor Branke]

Manche Spielchen werden nie alt. Nur die Spieler. Seufz!

[karlos3]

Alte ...

Moin!

[gkj43]

Moin ihrs!

[Schalker]

Moin

[Schalker]

Moin

[Foren-Rentner™]